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LP62S4096E-I Series
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History
Rev. No.
2.0
History
Change VCCmax from 3.3V to 3.6V Add product family and 55ns specification
Issue Date
January 25, 2002
Remark
(January, 2002, Version 2.0)
1
AMIC Technology, Inc.
LP62S4096E-I Series
512K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
n Power supply range: 2.7V to 3.6V n Access times: 55ns / 70ns (max.) n Current: Very low power version: Operating: 30mA (max.) Standby: 10A (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 2V (min.) n Available in 32-pin TSOP/TSSOP 36-ball CSP package
General Description
The LP62S4096E-I is a low operating current 4,194,304-bit static random access memory organized as 524,288 words by 8 bits and operates on a low power supply range: 2.7V to 3.3V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. n CE2 pin for CSP package only Power Dissipation Data Retention Standby Operating (ICCDR, Typ.) (ISB1, Typ.) (ICC2, Typ.) 0.08A 0.3A 5mA
Product Family
Product Family Operating Temperature -40C ~ +85C VCC Range 2.7V~3.6V Speed Package Type 32L TSOP 32L TSSOP 36B CSP
LP62S4096E-I
55ns / 70ns
1. Typical values are measured at VCC = 3.0V, TA = 25C and not 100% tested. 2. Data retention current VCC = 2.0V.
Pin Configurations
n TSOP/(TSSOP) n CSP (Chip Size Package) 36-pin Top View
16
1 1 A A0 I/O5 I/O6 GND VCC I/O7 I/O8 A9 OE A10 A18 CE1 A11 A17 A16 A12 A15 A13 2 A1 A2 3 CE2 WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O1 I/O2 VCC GND I/O3 I/O4 A14
LP62S4096EV-I (LP62S4096EX-I)
17 32
B C D E F G H
Pin No. Pin Name Pin No. Pin Name
1 A11 17 A3
2 A9 18 A2
3 A8 19 A1
4 A13 20 A0
5 WE 21 I/O1
6 A17 22 I/O2
7 A15 23 I/O3
8 VCC 24 GND
9 A18 25 I/O4
10 A16 26 I/O5
11 A14 27 I/O6
12 A12 28 I/O7
13 A7 29 I/O8
14 A6 30 CE1
15 A5 31 A10
16 A4 32 OE
(January, 2002, Version 2.0)
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AMIC Technology, Inc.
LP62S4096E-I Series
Block Diagram
A0 VCC GND A16 A17 A18 ROW DECODER 1024 X 4096 MEMORY ARRAY
I/O1
INPUT DATA CIRCUIT
COLUMN I/O
I/O8
CE1 CE2 OE WE
CONTROL CIRCUIT
Pin Description
Symbol A0 - A18 I/O1 - I/O8 GND CE1, CE2 OE WE VCC Description
Recommended DC Operating Conditions
(TA = -40C to + 85C) Symbol Address Inputs Data Input/Outputs Ground VIH Chip Enable VIL Output Enable Write Enable Power Supply CL TTL Input Low Voltage Output Load Output Load -0.3 0 +0.6 30 1 V pF Input High Voltage 2.2 VCC GND Parameter Supply Voltage Ground Min. 2.7 0 Typ. 3.0 0 Max. 3.6 0 VCC + 0.3 Unit V V V
(January, 2002, Version 2.0)
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AMIC Technology, Inc.
LP62S4096E-I Series
Absolute Maximum Ratings*
VCC to GND ------------------------------------- -0.5V to + 4.0V IN, IN/OUT Volt to GND--------------- -0.5V to VCC + 0.5V Operating Temperature, Topr -------------- -40C to + 85C Storage Temperature, Tstg --------------- -55C to + 125C Temperature Under Bias, Tbias ----------- -10C to + 85C Power Dissipation, PT --------------------------------------- 0.7W
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics
Symbol Parameter
(TA = -40C to + 85C, VCC = 2.7V to 3.6V, GND = 0V) LP62S4096E-55LLI / 70LLI Min. Typ. Max. 1 A VIN = GND to VCC CE1= VIH , CE2= VIL or OE = VIH WE =VIL VI/O = GND to VCC CE1= VIL, CE2= VIH II/O = 0mA Min. Cycle, Duty = 100%, CE1 = VIL CE2= VIH, II/O = 0mA CE1= VIL, CE2= VIH, VIH = VCC VIL = 0V, f = 1MHZ II/O = 0mA VCC 3.3V CE1= VIH, CE2= VIL VCC 3.3V CE1 VCC - 0.2V, or CE2 0.2V VIN 0.2V IOL = 2.1mA IOH = -1.0mA Unit Conditions
ILI ILO
Input Leakage Current
-
Output Leakage Current
-
-
1
A
ICC
Active Power Supply Current
-
-
5
mA
ICC1
Dynamic Operating Current
-
20
30
mA
ICC2
Dynamic Operating Current
-
5
15
mA
ISB
Standby Power
-
-
1
mA
ISB1
Supply Current
-
0.3
10
A
VOL VOH
Output Low Voltage Output High Voltage
2.2
-
0.4 -
V V
(January, 2002, Version 2.0)
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AMIC Technology, Inc.
LP62S4096E-I Series
Truth Table
Mode Standby Standby Output Disable Read Write Note: X = H or L CE1 H X L L L CE2 X L H H H
OE
X X H L X
WE
X X H H L
I/O Operation High Z High Z High Z DOUT DIN
Supply Current ISB, ISB1 ISB, ISB1 ICC, ICC1, ICC2 ICC, ICC1, ICC2 ICC, ICC1, ICC2
Capacitance (TA = 25C, f = 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 6 8 Unit pF pF Conditions VIN = 0V VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = -40C to + 85C, VCC = 2.7V to 3.6V)
Symbol Parameter LP62S4096E-55LLI Min. Read Cycle tRC tAA tACE1, tACE2 tOE tCLZ1, tCLZ2 tOLZ tCHZ1, tCHZ2 tOHZ tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change 55 10 5 0 0 5 55 55 30 20 20 70 10 5 0 0 5 70 70 35 25 25 ns ns ns ns ns ns ns ns ns Max. LP62S4096E-70LLI Min. Max. Unit
(January, 2002, Version 2.0)
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AMIC Technology, Inc.
LP62S4096E-I Series
AC Characteristics (continued)
Symbol Parameter LP62S4096E-55LLI Min. Write Cycle tWC tCW1 tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 55 50 0 50 40 0 0 25 0 5 25 70 60 0 60 50 0 0 30 0 5 25 ns ns ns ns ns ns ns ns ns ns Max. LP62S4096E-70LLI Min. Max. Unit
Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms Read Cycle 1(1)
tRC Address tAA
OE
tOE CE1 tOLZ5
tOH
CE2
tACE1 , tACE2 tCLZ1 , tCLZ2 DOUT
tOHZ 5 tCHZ1 , tCHZ2
(January, 2002, Version 2.0)
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AMIC Technology, Inc.
LP62S4096E-I Series
Timing Waveforms (continued)
Read Cycle 2
(1, 2, 4)
tRC Address
tAA tOH tOH
DOUT
Read Cycle 3
(1, 3, 4)
CS1
CS2
tACS1 , tACS2 tCLZ1 , tCLZ2
tCHZ1 , tCHZ2
DOUT
Notes: 1. 2. 3. 4. 5.
WE is high for Read Cycle. Device is continuously enabled, CE1 = VIL or CE2= VIH. Address valid prior to or coincident with CE1 transition low or CE2 transition high. OE = VIL. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested.
(January, 2002, Version 2.0)
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AMIC Technology, Inc.
LP62S4096E-I Series
Timing Waveforms (continued)
Write Cycle 1 (Write Enable Controlled)
tWC Address tAW tcw1 ,tcw2 CE1 (4) (6)
tWR3
CE2
tAS1
tWP2
WE
tDW
tDH
DIN tWHZ7 tOW7 DOUT
(January, 2002, Version 2.0)
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AMIC Technology, Inc.
LP62S4096E-I Series
Write Cycle 2 (Chip Enable Controlled)
tWC
Address
(6)
tAW
tAS1
tCW1 , tCW2
(4)
tWR3
CE1
CE2
2 tWP
WE
tDW DIN
tDH
tWHZ7 DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP) of a low CE1 or high CE2 , and a low WE . 3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low WE going high to the end of the Write cycle. 4. If the CE1 low or CE2 high transition occurs simultaneously with the WE low transition or after the WE transition , outputs remain in a high impedance state. 5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write. 6. OE level is high or low. 7. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested.
(January, 2002, Version 2.0)
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AMIC Technology, Inc.
LP62S4096E-I Series
AC Test Conditions
Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Levels Output Load 0.4V to 2.4V 5 ns 1.5V See Figures 1 and 2
TTL
TTL
CL 30pF
CL 5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ, tOHZ, tOL, tCHZ, tWHZ, and tOW
Data Retention Characteristics (TA = -40C to 85C)
Symbol VDR Parameter VCC for Data Retention Min. 2.0 Typ. Max. 3.6 Unit V Conditions CE1 VCC - 0.2V, or CE2 0.2V VCC = 2.0V, ICCDR Data Retention Current LL-Version 0.08 3* A CE1 VCC - 0.2V, or CE2 0.2V VIN 0V
tCDR tR tVR
Chip Disable to Data Retention Time Operation Recovery Time VCC Rising Time from Data Retention Voltage to Operating Voltage ICCDR: max.
0 tRC 5
-
-
ns ns ms See Retention Waveform
*
LP62S4096E-55LLI / 70LLI
1A at TA = 0C to + 40C
(January, 2002, Version 2.0)
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AMIC Technology, Inc.
LP62S4096E-I Series
Low VCC Data Retention Waveform (1) ( CE1 Controlled)
DATA RETENTION MODE
VCC
2.7V tCDR VDR 2V
2.7V tR
tVR
CE1 VIH CE1 VDR - 0.2V VIH
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE VCC 2.7V tCDR VDR 2V 2.7V tR tVR
CE2
VIL
CE2 0.2V
VIL
Ordering Information Part No.
LP62S4096EV-55LLI LP62S4096EX-55LLI LP62S4096EU-55LLI LP62S4096EV-70LLI LP62S4096EX-70LLI LP62S4096EU-70LLI
Access Time(ns)
55 55 55 70 70 70
Operating Current Max.(mA)
30 30 30 30 30 30
Standby Current Max.(uA)
10 10 10 10 10 10
Package
32L TSOP 32L TSSOP 36L CSP 32L TSOP 32L TSSOP 36L CSP
(January, 2002, Version 2.0)
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AMIC Technology, Inc.
LP62S4096E-I Series
Package Information TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
D
unit: inches/mm
e
A2
12.0 c A
GAUGE PLANE
E
A1
0.25 BSC
L LE
HD Detail "A" Detail "A"
y
D
S
b
0.10(0.004)
M
Symbol A A1 A2 b c D E e HD L LE S Y
Dimensions in inches 0.047 Max. 0.0040.002 0.0390.002 0.0080.001 0.0060.001 0.7240.004 0.3150.004 0.020 TYP. 0.7870.007 0.0200.004 0.031 TYP. 0.0167 TYP. 0.004 Max. 0 ~ 6
Dimensions in mm 1.20 Max. 0.100.05 1.000.05 0.200.03 0.150.02 18.400.10 8.000.10 0.50 TYP. 20.000.20 0.500.10 0.80 TYP. 0.425 TYP. 0.10 Max. 0 ~ 6
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.
(January, 2002, Version 2.0)
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AMIC Technology, Inc.
LP62S4096E-I Series
Package Information TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
e
12.0 A2 E c A
GAUGE PLANE
A1
0.25 BSC
L LE
D1 D Detail "A"
Detail "A"
D
0.10MM
S
SEATING PLANE
b
Symbol A A1 A2 b c E e D D1 L LE S y
Dimensions in inches 0.049 Max. 0.002 Min. 0.0390.002 0.0080.001 0.0060.0003 0.3150.004 0.020 TYP. 0.5280.008 0.4650.004 0.020.008 0.0266 Min. 0.0109 TYP. 0.004 Max. 0 ~ 6
Dimensions in mm 1.25 Max. 0.05 Min. 1.000.05 0.200.03 0.150.008 8.000.10 0.50 TYP. 13.400.20 11.800.10 0.500.20 0.675 Min. 0.278 TYP. 0.10 Max. 0 ~ 6
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.
(January, 2002, Version 2.0)
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AMIC Technology, Inc.
LP62S4096E-I Series
Package Information 36LD CSP (6 x 8 mm) Outline Dimensions
TOP VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER 123456 b (36X) 654321
unit: mm
A B C D E F G H e
A B C D E F G H
B A 0.10 C 0.20(4X)
E1
E
e D1 D
SIDE VIEW // 0.25 C
A2
C (0.36)
SEATING PLANE A1 A
Symbol A A1 A2 D E D1 E1 e b
Dimensions in mm MIN. 1.00 0.16 0.48 5.80 7.80 ------0.25 NOM. 1.10 0.21 0.53 6.00 8.00 3.75 5.25 0.75 0.30 MAX. 1.20 0.26 0.58 6.20 8.20 ------0.35
Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 4. BALL PAD OPENING OF SUBSTRATE IS 0.25mm (SMD) SUGGEST TO DESIGN THE PCB LAND SIZE AS 0.25mm (NSMD)
(January, 2002, Version 2.0)
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AMIC Technology, Inc.

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